{"id":2679,"date":"2019-06-28T00:34:59","date_gmt":"2019-06-28T00:34:59","guid":{"rendered":""},"modified":"2019-06-28T08:35:38","modified_gmt":"2019-06-28T00:35:38","slug":"fpga%e7%9a%84%e5%b7%a5%e4%bd%9c%e5%8e%9f%e7%90%86%e4%bb%a5%e5%8f%8a%e5%86%85%e9%83%a8%e7%bb%93%e6%9e%84","status":"publish","type":"post","link":"http:\/\/www.szryc.com\/?p=2679","title":{"rendered":"FPGA\u7684\u5de5\u4f5c\u539f\u7406\u4ee5\u53ca\u5185\u90e8\u7ed3\u6784"},"content":{"rendered":"<p style=\"margin-right: 0px; margin-bottom: 12px; margin-left: 0px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; margin-top: 0px !important; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\t<u style=\"color: rgb(51, 51, 51) !important;\">FPGA<\/u>\u91c7\u7528\u4e86\u903b\u8f91\u5355\u5143\u9635\u5217LCA(Logic Cell Array)\u8fd9\u6837\u4e00\u4e2a\u6982\u5ff5\uff0c\u5185\u90e8\u5305\u62ec\u53ef\u914d\u7f6e\u903b\u8f91\u6a21\u5757CLB(Configurable Logic Block)\u3001\u8f93\u51fa\u8f93\u5165\u6a21\u5757IOB(Input Output Block)\u548c\u5185\u90e8\u8fde\u7ebf(In<u style=\"color: rgb(51, 51, 51) !important;\">te<\/u>rconnect)\u4e09\u4e2a\u90e8\u5206\u3002 \u73b0\u573a\u53ef\u7f16\u7a0b\u95e8\u9635\u5217(FPGA)\u662f\u53ef<u style=\"color: rgb(51, 51, 51) !important;\">\u7f16\u7a0b\u5668<\/u>\u4ef6\u3002<\/p>\n<p align=\"center\" style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\t<img decoding=\"async\" alt=\"FPGA\u7684\u5de5\u4f5c\u539f\u7406\u4ee5\u53ca\u5185\u90e8\u7ed3\u6784\" src=\"http:\/\/www.szryc.com\/uploads\/allimg\/190628\/0S53T4E-0.jpg\" style=\"border: 0px; vertical-align: middle; cursor: pointer; margin: 0px auto; display: block; max-width: 100%; border-radius: 2px; height: 370px; width: 500px;\" \/><\/p>\n<div id=\"new-middle-berry\" style=\"margin: 0px 0px 15px; padding: 0px; color: rgb(51, 51, 51); word-wrap: break-word; font-size: 16px; font-family: \u5fae\u8f6f\u96c5\u9ed1;\">\n\t&nbsp;<\/div>\n<p style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\t\u4e0e\u4f20\u7edf\u903b\u8f91<u>\u7535\u8def<\/u>\u548c\u95e8\u9635\u5217(\u5982PAL\uff0cGAL\u53ca<u style=\"color: rgb(51, 51, 51) !important;\">CPLD<\/u>\u5668\u4ef6)\u76f8\u6bd4\uff0cFPGA\u5177\u6709\u4e0d\u540c\u7684\u7ed3\u6784\uff0cFPGA\u5229\u7528\u5c0f\u578b\u67e5\u627e\u8868(16&times;1<u style=\"color: rgb(51, 51, 51) !important;\">RAM<\/u>)\u6765\u5b9e\u73b0\u7ec4\u5408\u903b\u8f91\uff0c\u6bcf\u4e2a\u67e5\u627e\u8868\u8fde\u63a5\u5230\u4e00\u4e2aD<u style=\"color: rgb(51, 51, 51) !important;\">\u89e6\u53d1\u5668<\/u>\u7684\u8f93\u5165\u7aef\uff0c\u89e6\u53d1\u5668\u518d\u6765\u9a71\u52a8\u5176\u4ed6\u903b\u8f91\u7535\u8def\u6216\u9a71\u52a8<u style=\"color: rgb(51, 51, 51) !important;\">I\/O<\/u>\uff0c\u7531\u6b64\u6784\u6210\u4e86\u65e2\u53ef\u5b9e\u73b0\u7ec4\u5408\u903b\u8f91\u529f\u80fd\u53c8\u53ef\u5b9e\u73b0\u65f6\u5e8f\u903b\u8f91\u529f\u80fd\u7684\u57fa\u672c\u903b\u8f91\u5355\u5143\u6a21\u5757\uff0c\u8fd9\u4e9b\u6a21\u5757\u95f4\u5229\u7528\u91d1\u5c5e\u8fde\u7ebf\u4e92\u76f8\u8fde\u63a5\u6216\u8fde\u63a5\u5230I\/O\u6a21\u5757\u3002<\/p>\n<p style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\tFPGA\u7684\u903b\u8f91\u662f\u901a\u8fc7\u5411\u5185\u90e8\u9759\u6001<u style=\"color: rgb(51, 51, 51) !important;\">\u5b58\u50a8<\/u>\u5355\u5143\u52a0\u8f7d\u7f16\u7a0b\u6570\u636e\u6765\u5b9e\u73b0\u7684\uff0c\u5b58\u50a8\u5728<u style=\"color: rgb(51, 51, 51) !important;\">\u5b58\u50a8\u5668<\/u>\u5355\u5143\u4e2d\u7684\u503c\u51b3\u5b9a\u4e86\u903b\u8f91\u5355\u5143\u7684\u903b\u8f91\u529f\u80fd\u4ee5\u53ca\u5404\u6a21\u5757\u4e4b\u95f4\u6216\u6a21\u5757\u4e0eI\/O\u95f4\u7684\u8054\u63a5\u65b9\u5f0f\uff0c\u5e76\u6700\u7ec8\u51b3\u5b9a\u4e86FPGA\u6240\u80fd\u5b9e\u73b0\u7684\u529f\u80fd\uff0cFPGA\u5141\u8bb8\u65e0\u9650\u6b21\u7684\u7f16\u7a0b.<\/p>\n<p style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\t\u91c7\u7528FPGA\u8bbe\u8ba1<u style=\"color: rgb(51, 51, 51) !important;\">ASIC<\/u>\u7535\u8def(\u4e13\u7528<u style=\"color: rgb(51, 51, 51) !important;\">\u96c6\u6210\u7535\u8def<\/u>)\uff0c\u7528\u6237\u4e0d\u9700\u8981\u6295\u7247\u751f\u4ea7\uff0c\u5c31\u80fd\u5f97\u5230\u5408\u7528\u7684\u82af\u7247\u3002FPGA\u53ef\u505a\u5176\u5b83\u5168\u5b9a\u5236\u6216\u534a\u5b9a\u5236ASIC\u7535\u8def\u7684\u4e2d\u8bd5\u6837\u7247\u3002FPGA\u5185\u90e8\u6709\u4e30\u5bcc\u7684\u89e6\u53d1\u5668\u548cI\/O\u5f15\u811a\u3002FPGA\u662fASIC\u7535\u8def\u4e2d\u8bbe\u8ba1\u5468\u671f\u6700\u77ed\u3001\u5f00\u53d1\u8d39\u7528\u6700\u4f4e\u3001\u98ce\u9669\u6700\u5c0f\u7684\u5668\u4ef6\u4e4b\u4e00\u3002FPGA\u91c7\u7528\u9ad8\u901fCMOS\u5de5\u827a\uff0c\u529f\u8017\u4f4e\uff0c\u53ef\u4ee5\u4e0eCMOS\u3001TTL\u7535\u5e73\u517c\u5bb9\u3002<\/p>\n<p style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\t\u53ef\u4ee5\u8bf4\uff0cFPGA\u82af\u7247\u662f\u5c0f\u6279\u91cf\u7cfb\u7edf\u63d0\u9ad8\u7cfb\u7edf\u96c6\u6210\u5ea6\u3001\u53ef\u9760\u6027\u7684\u6700\u4f73\u9009\u62e9\u4e4b\u4e00\u3002FPGA\u662f\u7531\u5b58\u653e\u5728\u7247\u5185RAM\u4e2d\u7684\u7a0b\u5e8f\u6765\u8bbe\u7f6e\u5176\u5de5\u4f5c\u72b6\u6001\u7684\uff0c\u56e0\u6b64\uff0c\u5de5\u4f5c\u65f6\u9700\u8981\u5bf9\u7247\u5185\u7684RAM\u8fdb\u884c\u7f16\u7a0b\u3002\u7528\u6237\u53ef\u4ee5\u6839\u636e\u4e0d\u540c\u7684\u914d\u7f6e\u6a21\u5f0f\uff0c\u91c7\u7528\u4e0d\u540c\u7684\u7f16\u7a0b\u65b9\u5f0f\u3002<\/p>\n<p align=\"center\" style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\t<img decoding=\"async\" alt=\"FPGA\u7684\u5de5\u4f5c\u539f\u7406\u4ee5\u53ca\u5185\u90e8\u7ed3\u6784\" src=\"http:\/\/www.szryc.com\/uploads\/allimg\/190628\/0S53TH5-1.png\" style=\"border: 0px; vertical-align: middle; cursor: pointer; margin: 0px auto; display: block; max-width: 100%; border-radius: 2px; width: 500px; height: 398px;\" \/><\/p>\n<p style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\t\u52a0\u7535\u65f6\uff0cFPGA\u82af\u7247\u5c06EP<u style=\"color: rgb(51, 51, 51) !important;\">ROM<\/u>\u4e2d\u6570\u636e\u8bfb\u5165\u7247\u5185\u7f16\u7a0bRAM\u4e2d\uff0c\u914d\u7f6e\u5b8c\u6210\u540e\uff0cFPGA\u8fdb\u5165\u5de5\u4f5c\u72b6\u6001\u3002\u6389\u7535\u540e\uff0cFPGA\u6062\u590d\u6210\u767d\u7247\uff0c\u5185\u90e8\u903b\u8f91\u5173\u7cfb\u6d88\u5931\uff0c\u56e0\u6b64\uff0cFPGA\u80fd\u591f\u53cd\u590d\u4f7f\u7528\u3002FPGA\u7684\u7f16\u7a0b\u65e0\u987b\u4e13\u7528\u7684FPGA\u7f16\u7a0b\u5668\uff0c\u53ea\u987b\u7528\u901a\u7528\u7684EPROM\u3001PROM\u7f16\u7a0b\u5668\u5373\u53ef\u3002\u5f53\u9700\u8981\u4fee\u6539FPGA\u529f\u80fd\u65f6\uff0c\u53ea\u9700\u6362\u4e00\u7247EPROM\u5373\u53ef\u3002\u8fd9\u6837\uff0c\u540c\u4e00\u7247FPGA\uff0c\u4e0d\u540c\u7684\u7f16\u7a0b\u6570\u636e\uff0c\u53ef\u4ee5\u4ea7\u751f\u4e0d\u540c\u7684\u7535\u8def\u529f\u80fd\u3002\u56e0\u6b64\uff0cFPGA\u7684\u4f7f\u7528\u975e\u5e38\u7075\u6d3b\u3002<\/p>\n<p style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\tFPGA\/CPLD\u7ed3\u6784\u7531\u4e09\u5927\u90e8\u5206\u7ec4\u6210\uff1a<\/p>\n<p style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\t1.\u4e00\u4e2a\u4e8c\u7ef4\u7684\u903b\u8f91\u5757\u9635\u5217\uff0c\u6784\u6210\u4e86PLD\u5668\u4ef6\u7684\u903b\u8f91\u7ec4\u6210\u6838\u5fc3\u3002<\/p>\n<p style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\t2.\u8f93\u5165\/\u8f93\u51fa\u5757\u3002<\/p>\n<p style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\t3.\u8fde\u63a5\u903b\u8f91\u5757\u7684\u53ef\u7f16\u7a0b\u5185\u90e8\u8fde\u7ebf\u8d44\u6e90\u3002\u8fde\u7ebf\u8d44\u6e90\uff1a\u7531\u5404\u79cd\u957f\u5ea6\u7684\u8fde\u7ebf\u7ebf\u6bb5\u7ec4\u6210\uff0c\u5176\u4e2d\u6709\u4e00\u4e9b\u53ef\u7f16\u7a0b\u7684\u8fde\u63a5<u style=\"color: rgb(51, 51, 51) !important;\">\u5f00\u5173<\/u>\uff0c\u5b83\u4eec\u7528\u4e8e\u903b\u8f91\u5757\u4e4b\u95f4\u3001\u903b\u8f91\u5757\u4e0e\u8f93\u5165\/\u8f93\u51fa\u5757\u4e4b\u95f4\u7684\u8fde\u63a5\u3002Fpga\u7684\u5185\u90e8\u89c4\u6a21\u975e\u5e38\u5927\uff0c\u5185\u90e8\u76f8\u5f53\u4e8e\u51e0\u5343\u5757\u901a\u7528IC\u82af\u7247\u3002<\/p>\n<p style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\tFPGA\u7684\u591a\u79cd\u914d\u7f6e\u6a21\u5f0f\uff1a\u5e76\u884c\u4e3b\u6a21\u5f0f\u4e3a\u4e00\u7247FPGA\u52a0\u4e00\u7247EPROM\u7684\u65b9\u5f0f;\u4e3b\u4ece\u6a21\u5f0f\u53ef\u4ee5\u652f\u6301\u4e00\u7247PROM\u7f16\u7a0b\u591a\u7247FPGA;\u4e32\u884c\u6a21\u5f0f\u53ef\u4ee5\u91c7\u7528\u4e32\u884cPROM\u7f16\u7a0bFPGA;\u4ee5\u53ca\u5916\u8bbe\u6a21\u5f0f\u3002<\/p>\n<p style=\"margin: 0px 0px 12px; padding: 0px; word-wrap: break-word; letter-spacing: 0.5px; font-size: 16px; text-indent: 2em; color: rgb(51, 51, 51) !important; line-height: 30px !important; font-family: &quot;Microsoft yahei&quot;, \u5fae\u8f6f\u96c5\u9ed1 !important;\">\n\t\u5916\u8bbe\u6a21\u5f0f\u53ef\u4ee5\u5c06FPGA\u4f5c\u4e3a\u5fae\u5904\u7406\u5668\u7684\u5916\u8bbe\uff0c\u7531\u5fae\u5904\u7406\u5668\u5bf9\u5176\u7f16\u7a0b\u3002\u3000\u3000\u5982\u4f55\u5b9e\u73b0\u5feb\u901f\u7684\u65f6\u5e8f\u6536\u655b\u3001\u964d\u4f4e\u529f\u8017\u548c\u6210\u672c\u3001\u4f18\u5316<u style=\"color: rgb(51, 51, 51) !important;\">\u65f6\u949f<\/u>\u7ba1\u7406\u5e76\u964d\u4f4eFPGA\u4e0e<u>PCB<\/u>\u5e76\u884c\u8bbe\u8ba1\u7684\u590d\u6742\u6027\u7b49\u95ee\u9898\uff0c\u4e00\u76f4\u662f\u91c7\u7528FPGA\u7684\u7cfb\u7edf\u8bbe\u8ba1\u5de5\u7a0b\u5e08\u9700\u8981\u8003\u8651\u7684\u5173\u952e\u95ee\u9898\u3002\u5982\u4eca\uff0c\u968f\u7740FPGA\u5411\u66f4\u9ad8\u5bc6\u5ea6\u3001\u66f4\u5927\u5bb9\u91cf\u3001\u66f4\u4f4e\u529f\u8017\u548c\u96c6\u6210\u66f4\u591aIP\u7684\u65b9\u5411\u53d1\u5c55\uff0c\u7cfb\u7edf\u8bbe\u8ba1\u5de5\u7a0b\u5e08\u5728\u4ece\u8fd9\u4e9b\u4f18\u5f02\u6027\u80fd\u83b7\u76ca\u7684\u540c\u65f6\uff0c\u4e0d\u5f97\u4e0d\u9762\u5bf9\u7531\u4e8eFPGA\u524d\u6240\u672a\u6709\u7684\u6027\u80fd\u548c\u80fd\u529b\u6c34\u5e73\u800c\u5e26\u6765\u7684\u65b0\u7684\u8bbe\u8ba1\u6311\u6218\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"<p>FPGA \u91c7\u7528\u4e86\u903b\u8f91\u5355\u5143\u9635\u5217LCA(Logic Cell Array)\u8fd9\u6837\u4e00\u4e2a\u6982\u5ff5\uff0c\u5185\u90e8\u5305\u62ec\u53ef\u914d\u7f6e\u903b\u8f91\u6a21\u5757CLB(Configurable Logic Block)\u3001\u8f93\u51fa\u8f93\u5165\u6a21\u5757IOB(Input Output Block)\u548c\u5185\u90e8\u8fde\u7ebf(In te rconnect)\u4e09\u4e2a\u90e8\u5206\u3002 \u73b0\u573a\u53ef\u7f16\u7a0b<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[14],"tags":[],"_links":{"self":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/2679"}],"collection":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=2679"}],"version-history":[{"count":0,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/2679\/revisions"}],"wp:attachment":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=2679"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=2679"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=2679"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}