\n\t\u521d\u59cb\u5316SP<\/p>\n
\n\tSPI_InitStructure.SPI_Directi<\/u>on = SPI_DirecTIon_2Lines_FullDuplex; \/\/\u5168\u53cc\u5de5<\/p>\n
\n\tSPI_InitStructure.SPI_Mode = SPI_Mode_Maste<\/u>r; \/\/\u4e3b\u6a21\u5f0f<\/p>\n
\n\tSPI_InitStructure.SPI_DataSize = SPI_DataSize_16b; \/\/16bit\u5bbd\u5ea6<\/p>\n
\n\tSPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;<\/p>\n
\n\tSPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;<\/p>\n
\n\tSPI_InitStructure.SPI_NSS = SPI_NSS_Soft;<\/p>\n
\n\t![\"STM32\u5355\u7247\u673aSPI\u603b\u7ebf\u4e0eFPGA\u7684\u901a\u4fe1\u8bbe\u8ba1\"](\"http:\/\/www.szryc.com\/uploads\/allimg\/190606\/15463V359-0.jpg\")
<\/p>\n
\n\tSPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; \/\/2--18MHz; 4--9MHz; 8--4.5MHz<\/p>\n
\n\tSPI_InitStructure.SPI_Firs<\/u>tBit = SPI_FirstBit_MSB; \/\/\u9ad8\u4f4d\u5728\u524d<\/p>\n
\n\tSPI_InitStructure.SPI_CRCPolynomi<\/u>al = 7;<\/p>\n
\n\tSPI_Init\uff08SPIx\uff0c &SPI_InitStructure\uff09;<\/p>\n
\n\tSPI_Cmd\uff08SPIx\uff0c ENABLE\uff09;<\/p>\n
\n\tSPI\u4e0d\u80fd\u786c\u4ef6\u63a7\u5236CS\uff0c\u53ea\u80fd\u8f6f\u4ef6\u6765\u63a7\uff0c\u5c31\u662f\u901a\u8fc7\u5c06NSS\u8bbe\u4e3a\u5916\u90e8GPIO\u6765\u63a7\u5236\u3002<\/p>\n
\n\t\u50cf\u6211\u6240\u505a\u7684\u9879\u76ee\u662f\u4f7f\u7528STM32<\/u>\u4e0eFPGA<\/u>\u901a\u4fe1\uff0c\u800cFPGA\u7684SPI\u5de5\u4f5c\u5728\u8fd9\u79cd\u4e00\u76f4\u72b6\u6001<\/p>\n
\n\t\u4f5c\u4e3a\u4e3b\u8bbe\u5907\u7684STM32\uff0cCS\u5728\u4f20\u8f93\u6570\u636e\u7684\u65f6\u5019\u4e3a\u4f4e\uff0c\u4f20\u8f93\u5b8c\u6bd5\u540e\u5fc5\u987b\u62c9\u9ad8\uff0c\u8fd9\u6837FPGA\u53ef\u4ee5\u5224\u65ad\u51faSPI\u7684\u4f20\u8f93\u8d77\u6b62\u72b6\u6001\u3002<\/p>\n
\n\tFPGA\u7684\u6570\u636e\u4f20\u8f93\u683c\u5f0f\u662f16bit\u5730\u5740+16bit\u6570\u636e<\/p>\n
\n\t\u5bf9\u4e8e\u8bfb16bit\uff0c\u5b9e\u73b0\u5982\u4e0b<\/p>\n
\n\tuint16_t spi_read\uff08SPI_TypeDef* SPIx\uff0cuint32_t addr\uff09<\/p>\n
\n\t{<\/p>\n
\n\tuint16_t value;<\/p>\n
\n\tuint16_t spi_nss;<\/p>\n
\n\tuint16_t add;<\/p>\n
\n\tuint32_t level;<\/p>\n
\n\tif\uff08SPI1 == SPIx\uff09<\/p>\n
\n\tspi_nss = SPI1_PIN_NSS;<\/p>\n
\n\telse if\uff08SPI2 == SPIx\uff09<\/p>\n
\n\tspi_nss = SPI2_PIN_NSS;<\/p>\n
\n\twhile \uff08SPI_I2S_GetFlagStatus\uff08SPIx\uff0c SPI_I2S_FLAG_TXE\uff09 == RESET\uff09;<\/p>\n
\n\tGPIO_ResetBits\uff08GPIOA\uff0c spi_nss\uff09;<\/p>\n
\n\tSPI_I2S_SendData\uff08SPIx\uff0c addr\uff09; \/\/0xf014 \u300b\u300b 2<\/p>\n
\n\twhile \uff08SPI_I2S_GetFlagStatus\uff08SPIx\uff0c SPI_I2S_FLAG_TXE\uff09 == RESET\uff09;<\/p>\n
\n\tSPI_I2S_SendData\uff08SPIx\uff0c 0x0\uff09;<\/p>\n
\n\twhile \uff08SPI_I2S_GetFlagStatus\uff08SPIx\uff0c SPI_I2S_FLAG_RXNE\uff09 == RESET\uff09;<\/p>\n
\n\tSPI_I2S_ReceiveDa<\/u>ta\uff08SPIx\uff09;<\/p>\n
\n\twhile \uff08SPI_I2S_GetFlagStatus\uff08SPIx\uff0c SPI_I2S_FLAG_TXE\uff09 == RESET\uff09;<\/p>\n
\n\tGPIO_SetBits\uff08GPIOA\uff0c spi_nss\uff09;<\/p>\n
\n\twhile \uff08SPI_I2S_GetFlagStatus\uff08SPIx\uff0c SPI_I2S_FLAG_RXNE\uff09 == RESET\uff09;<\/p>\n
\n\tvalue = SPI_I2S_ReceiveData\uff08SPIx\uff09;<\/p>\n
\n\treturn value;<\/p>\n
\n\t}<\/p>\n
\n\t\u5199\u51fd\u6570<\/p>\n
\n\tvoid spi_write\uff08SPI_TypeDef* SPIx\uff0cuint32_t addr\uff0c uint16_t value\uff09<\/p>\n
\n\t{<\/p>\n
\n\tuint16_t spi_nss;<\/p>\n
\n\tuint32_t level;<\/p>\n
\n\tif\uff08SPI1 == SPIx\uff09<\/p>\n
\n\tspi_nss = SPI1_PIN_NSS;<\/p>\n
\n\telse if\uff08SPI2 == SPIx\uff09<\/p>\n
\n\tspi_nss = SPI2_PIN_NSS;<\/p>\n
\n\twhile \uff08SPI_I2S_GetFlagStatus\uff08SPIx\uff0c SPI_I2S_FLAG_TXE\uff09 == RESET\uff09;<\/p>\n
\n\tGPIO_ResetBits\uff08GPIOA\uff0c spi_nss\uff09;<\/p>\n
\n\tSPI_I2S_SendData\uff08SPIx\uff0c addr\uff09;<\/p>\n
\n\twhile \uff08SPI_I2S_GetFlagStatus\uff08SPIx\uff0c SPI_I2S_FLAG_TXE\uff09 == RESET\uff09;<\/p>\n
\n\tSPI_I2S_SendData\uff08SPIx\uff0c value\uff09;<\/p>\n
\n\twhile \uff08SPI_I2S_GetFlagStatus\uff08SPIx\uff0c SPI_I2S_FLAG_RXNE\uff09 == RESET\uff09;<\/p>\n
\n\tSPI_I2S_ReceiveData\uff08SPIx\uff09;<\/p>\n
\n\twhile \uff08SPI_I2S_GetFlagStatus\uff08SPIx\uff0c SPI_I2S_FLAG_TXE\uff09 == RESET\uff09;<\/p>\n
\n\tGPIO_SetBits\uff08GPIOA\uff0c spi_nss\uff09;<\/p>\n
\n\twhile \uff08SPI_I2S_GetFlagStatus\uff08SPIx\uff0c SPI_I2S_FLAG_RXNE\uff09 == RESET\uff09;<\/p>\n
\n\tSPI_I2S_ReceiveData\uff08SPIx\uff09;<\/p>\n
\n\t}<\/p>\n
\n\t\u62ffwrite\u51fd\u6570\u4e3e\u4f8b<\/p>\n
\n\t\u53ea\u6240\u4ee5\u8fd9\u4e48\u8bbe\u8ba1\u662f\u56e0\u4e3a<\/p>\n
\n\t\u5982\u679c\u662f\u51fd\u6570\u4e00\u5f00\u59cb\u5c31\u5c06NSS\u811a\u62c9\u4f4e\uff0c\u7136\u540e\u518d\u53bbsend\uff0c\u5982\u4e0b<\/p>\n
\n\tGPIO_ResetBits\uff08GPIOA\uff0c spi_nss\uff09;<\/p>\n
\n\twhile \uff08SPI_I2S_GetFlagStatus\uff08SPIx\uff0c SPI_I2S_FLAG_TXE\uff09 == RESET\uff09;<\/p>\n
\n\tSPI_I2S_SendData\uff08SPIx\uff0c addr\uff09;<\/p>\n
\n\t\u8fd9\u6837\u5728CS\u62c9\u4f4e\u4e00\u6bb5\u65f6\u95f4\u540e\uff08\u65f6\u95f4\u5927\u6982\u670916\u4e2a\u65f6\u949f\u5468\u671f\uff09\uff0c\u624d\u6709CLK\uff0c\u8fd9\u6837\u5ef6\u65f6\u5c31\u4f1a\u964d\u4f4eSPI\u7684\u4f20\u8f93\u6548\u7387<\/p>\n
\n\t\u4e4b\u524d\u90a3\u79cd\u65b9\u5f0f\u4f1a\u5728CS\u62c9\u5e95\u540e\u5f88\u5feb\u5c31\u6709clk\u65f6\u949f\u51fa\u6765<\/p>\n
\n\t\u4e4b\u6240\u4ee5\u5199\u4e24\u6b21\u518d\u8bfb\u4e24\u6b21\u800c\u4e0d\u662f\u8bfb\u4e00\u6b21\u5199\u4e00\u6b21\u4e5f\u662f\u8003\u8651\u5230\u6548\u7387\u7684\u95ee\u9898<\/p>\n
\n\t\u5982\u679c\u5148\u5199\u4e00\u6b21\u518d\u8bfb\u4e00\u6b21\uff0c\u770b\u6ce2\u5f62\u6bcf\u4e2a\u6570\u636e\u4e4b\u95f4\u6709\u6bd4\u8f83\u5927\u7684\u7a7a\u9699\u662f\u6ca1\u6709clk\u7684\uff0c\u5c31\u662f\u8bf4\u5728\u4f20\u8f93\u5b8c\u4e00\u4e2a\u6570\u636e\u540e\u518d<\/p>\n
\n\t\u4f20\u7b2c\u4e8c\u4e2a\u4f1a\u8981\u7b49\u4e00\u6bb5\u65f6\u95f4\uff0c\u8fd9\u4e2a\u5bf9\u901f\u5ea6\u8981\u6c42\u6bd4\u8f83\u9ad8\u7684\u8bbe\u5907\u662f\u4e0d\u5141\u8bb8\u7684<\/p>\n
\n\t\u8fd8\u6709\u503c\u5f97\u6ce8\u610f\u7684\u662f\uff1a<\/p>\n
\n\t\u5982\u679cSPI\u662f\u4e3b\u6a21\u5f0f\uff0c\u90a3\u4e48GPIO\u8bbe\u7f6e\u4e3a<\/p>\n
\n\tNSS\u662fGPIO_Mode_Out_PP<\/p>\n
\n\tCLK\u662fGPIO_Mode_AF_PP<\/p>\n
\n\tMOSI\u662fGPIO_Mode_AF_PP<\/p>\n
\n\tMISO\u662fGPIO_Mode_IN_FLOATING<\/p>\n
\n\t\u5982\u679cSPI\u662f\u4ece\u6a21\u5f0f\uff0c\u90a3\u4e48GPIO\u8bbe\u7f6e\u4e3a<\/p>\n
\n\tNSS\u662fGPIO_Mode_Out_PP<\/p>\n
\n\tCLK\u662fGPIO_Mode_IN_FLOATING<\/p>\n
\n\tMOSI\u662fGPIO_Mode_IN_FLOATING<\/p>\n
\n\tMISO\u662fGPIO_Mode_AF_PP<\/p>\n","protected":false},"excerpt":{"rendered":"
\u6700\u8fd1\u5728\u7814\u7a76S PI \u603b\u7ebf\uff0c\u81f3\u4e8e\u534f\u8bae\u548c\u786c\u4ef6\u63cf\u8ff0\u5c31\u4e0d\u591a\u8bf4\u4e86 \u56db\u7ebf\u5305\u62ec \u65f6\u949f \u3001\u7247\u9009\u3001\u63a5\u6536\u3001\u53d1\u9001 \u521d\u59cb\u5316SP SPI_InitStructure.SPI_Direc ti on = SPI_DirecTIon_2Lines_FullDuplex; \/\/\u5168\u53cc\u5de5 SPI_InitStructure.SPI_Mode<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[14],"tags":[],"_links":{"self":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/2605"}],"collection":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=2605"}],"version-history":[{"count":0,"href":"http:\/\/www.szryc.com\/index.php?rest_route=\/wp\/v2\/posts\/2605\/revisions"}],"wp:attachment":[{"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=2605"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=2605"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.szryc.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=2605"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}